Channelized Receiver Platform of SDR Based on FPGAs

【摘要】：正 In this paper, a channelized receiver platform of software defined radio is developed which is mainly to realize wideband quadrature digitization, modulation classification and demodulation exploiting A/D Converters. FPGAs with the combination of programmable DSPs. The front-end of researched receiver based on polyphase filter quadrature digitization processors, where digitization takes place at intermediate frequencies (IF), adopts a wideband design with a bandwidth of up to 100MHz and a centered carrier frequeney of up to 250MHz. And the low-complexity high-speed digital IF signal processing is carried out with CORD1C algorithm on FPGAs. then to realize the recognition of several modulation schemes such as 2ASK. 4ASK. 2PSK. 4PSK 2FSK. 4FSK, 16QAM to implement communication protocols fairly flexibly.