REED-MULLER EXPANSIONS FOR SWITCHING FUNCTION SYNTHESIS
【摘要】:正 New technologies offered by FPGA circuits to realise ASIC devices mean that exclusive-OR logic can be used within logic synthesis without any resource penalty. This paper describes a new heuristic for computing RM expansions from inclusive-OR sums of products, which is a key problem in this area. The algorithm finds a polarity of variables which leads to quasi-minimal fixed polarity RM expansions.
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