A CONSISTENT APPROACH IN LOGIC SYNTHESIS FOR FPGA ARCHITECTURES
【摘要】：正 We present an efficient optimization mapping approach for FPGA (Field Programmable Gate Array) synthesis. Tfiis approach is made possible by using very fast techniques based on multi-ROBDD (Shared, Reduced and Ordered Binary Decision Diagrams) representation for boolean functions. We have developed a Multi-ROBDD optimization procedure guided by cost functions corresponding to the target FPGA architectures. We present results on the two most popular FPGA architectures (Xilinx and Actel) and we compare our results with Sis .