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《Digest of Papers of 7th Workshop on RTL and High Level Testing》2006年
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Designing Power-aware Wrappers for Multi-clock Domain Cores Using Clock Domain Partitioning

Thomas Edison Yu  Tomokazu Yoneda  Danella Zhao  Hideo Fujiwara  
【摘要】:正This paper presents a method for designing power-aware test wrappers for embedded cores with multiple clock domains. We make use of partitioning of the clock domains into smaller sub-domains in combination with bandwidth conversion, multiple shift frequencies and gated-clocks to achieve greater flexibility when determining an optimal test schedule under tight power constraints.

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